The present invention relates to multi-chip devices, and more particularly to decapsulation techniques for multi-chip devices.
Innovations in integrated circuit devices have led to the formation of a multi-chip package. An example of a multi-chip package is a stacked die configuration consisting of a (DIE 1) top die 10, e.g., a Flash memory die, attached via an adhesive 12 to a (DIE 2) bottom die 14, e.g., an SRAM die, mounted on a substrate 16, e.g., BT (Bismaleimide Triazine) resin, in an FBGA (Fine Ball Grid Array) package 18, as shown in the cross-section illustration of FIG. 1. Each die is wire bonded to an interposer 20, e.g., copper foil, via wire bonds 22 and 24. A design restriction in this structure requires the top die 10 to be smaller than the bottom die 14, which allows space for wire bonding for the bottom die. Advantageously, with the multi-chip package, the dies share common address and data buses, allowing for a package with a low pin count.
For performing failure analysis on the top die (DIE 1) 10 of this type of package, the techniques utilized on conventional packages can still be used, with package decapsulation performed using a commercial chemical automatic jet-etch decapper (autodecapper). However, if failure analysis is required on the bottom die (DIE 2) 14, it is a challenge to remove the top die 10 while keeping the bottom die 14 fully functional for further analysis.
Accordingly, what is needed is a system and method for a new technique to achieve removal of a top die without damaging the bottom die in a multi-chip package in order to retain full failure analysis capability on these types of packaged devices. The present invention addresses such a need.
Aspects for performing decapsulation of multi-chip devices are presented. One aspect includes removing a top die of the multi-chip device without employing a wet chemical etch and removing residual attach and package materials to expose a bottom die of the multi-chip device. An alternate aspect includes utilizing mechanical polishing and wet chemical etching to remove a top die of the multi-chip device, and exposing a bottom die through chemical decapsulation to allow failure analysis of the bottom die. A Flash memory die as a top die and a static random access memory (SRAM) die as a bottom die are included as a multi-chip device capable of decapsulation through these aspects.
With the present invention, alternate techniques of decapsulation for stacked die integrated circuit devices are provided. In the preferred aspects, mechanical polishing is employed at least once during the removal of a top die to reduce the possibility of overetching a bottom die. Thus, the present invention maintains the integrity of the bottom die to allow failure analysis of the bottom die in a straightforward and effective manner. These and other advantages of the present invention will be more filly understood in conjunction with the following detailed description and accompanying drawings.